Very large scale integrated circuits, also known as VLSI circuits or chips, at the present time are fine small plates of substantially square semiconductor material, more than 1 cm on a side, provided with a great number of input/output terminals, on the order of 300 to 400. In TAB technology (tape-automated bonding), each integrated circuit is mounted on a substrate comprising an insulating sheet in which a window is provided with leads arranged in an overhanging fashion in order to be connected, inside the window, to the input/output terminals of the integrated circuit. These terminals are therefore located on the periphery of the integrated circuit, either in a line or in staggered fashion. Ordinarily, the insulating sheet of the substrate forms a flexible tape provided with successive windows for mounting the integrated circuits and with perforations on the side for the displacement and positioning of the tape. Current terminology calls this tape a TAB tape, and the bundle of leads disposed overhangingly about each window is known as a spider. Manipulation of the substrate is done directly on the TAB tape or by way of a rigid frame. One rigid frame that is widely used is the type used to hold photographic slides, such as are described for instance in U.S. Pat. Nos. 4,007,479 and 4,069,496. In this frame, a portion of the TAB tape relating to one integrated circuit and its spider is positioned by means of the lateral perforations of the tape.
A TAB substrate for an integrated circuit has several applications. First, it serves to mount an integrated circuit on the free inner ends of the leads of the spider, by an operation known as ILB (inner lead bonding). It is then used to make tests of the integrated circuit, by applying test points to the contact zones formed by the outer ends of the leads of the spider on the substrate sheet. A distinction is made between simple tests for verifying the ILB soldering or checking the function of the integrated circuit, and elaborate tests such as to determine the reliability of the integrated circuit over time by way of accelerated aging (known as "burn-in"). Finally, one known application for a TAB substrate of an integrated circuit comprises cutting the leads of the spider in one window of the substrate, to enable picking up the integrated circuit, provided with its corresponding leads there, and fixing the ends of these leads to the respective zones of an interconnection substrate, such as a multilayer printed circuit board. This operation is known as OLB (outer lead bonding). At the present time, the spider, cut away from its substrate, is mounted in a package for its OLB connection to an interconnection substrate. On the printed wiring boards, the connection zones and the outer conductive portions are typically coated with a layer of tin-lead, and can then be easily soldered to a spider, if the spider is adapted to this type of soldering. The adaptation comprises simply uniformly tinning the entire outer surface of the leads of the spider. However, to adapt large scale integration spiders to tin-lead soldering presents problems, at present.
The first problem is to achieve uniform tinning of a spider intended for a very large scale integrated circuit, the leads of which are necessarily quite narrow and very close to one another. For example, for an integrated circuit having more than 300 input/output terminals, their spacing on the chip may be less than 100 .mu.m, and the leads in the area of the OLB soldering zone may have a width of 100 .mu.m, resulting in a spacing of equal value. Under these conditions, defects in coverage of the leads with the tin, such as filaments, spikes or blobs, either cause short circuits or tend to come into contact with the adjacent leads in the course of the ILB and OLB bonding, which easily interrupts the regularity in spacing of the leads. The solution presently used comprises covering the copper leads with gold, using bonding materials such as nickel, for example, as an intermediary.
The second problem in uniform tinning is encountered when the ILB connection of the spider is done on gold beads deposited on the input/output terminals of the chip. Eutectic gold-tin soldering can create intermetallic compounds that alter the mechanical and electrical properties of the soldering. This defect is even more undesirable, the smaller the surface area of the soldering. Gold-plating of the spider assures a reliable ILB connection by thermocompression on the gold beads of the integrated circuit.
The third problem in tinning a spider is in terms of the contact zones made at the outer ends of the spider and arises in the course of an elaborate functional test, such as that done after accelerated aging testing of the integrated circuit (burn-in). Aging of the integrated circuit translates into oxidation or alteration of the contact zones, if they are not gold-plated, and makes for wrong the measurements of the electrical test because of the possible wrong contacts of the test sensors with the zones.
Hence, the solution common to all these three problems is uniform gold-plating of the spiders. However, OLB soldering of a TAB spider on the normally tinned zones of a printed wiring board remains problematic because of the intermetallic compounds at the time of eutectic gold-tin soldering. Adapting a gold-plated spider to the OLB operation on a printed wiring board would thus comprise plating the zones of the board with the gold, which must be of a certain purity so as to be suitable for soldering by thermocompression. Selective gold-plating of the printed wiring boards would necessarily encounter technical difficulties that most often entail prohibitive cost.
In summary, a user wishing to avail himself of TAB substrates for very large scale chips, for wide distribution and at low cost, would have to choose between bare spiders, without tinning or without gold-plating, or completely gold-plated spiders.